A Novel Technique for Making QEMU an Instruction Set Simulator for Co-simulation with SystemC

This paper presents a novel technique for converting QEMU from a virtual machine into an instructionaccurate instruction set simulator (IA-ISS) and using it as the processor model of a QEMU and SystemC-based virtual platform. The proposed framework can not only simulate arbitrary hardware modeled in SystemC, but it can also be used to evaluate the performance of the target system for SoC development. Our experimental results show that the built-in vector interrupt controller of QEMU modeled in C can be easily replaced by one modeled in SystemC for demonstrating the waveform of AMBA on-chip-bus model connected with the adapted IA-ISS. Moreover, the instruction-accurate statistics can be gathered while co-simulating with a full-fledged Linux kernel. Our experimental results further show that with every instruction executed and every memory accessed since power on traced, the hardware/software co-simulation takes no more than 16 minutes in booting up the Linux kernel, even in the worst case.